1. Field of the Invention
This invention relates to processes for manufacturing integrated circuits, and in particular, to a process for fabricating integrated circuits having both bipolar and complementary field effect transistors on a common substrate. The process is particularly suited to the manufacture of high performance products, for example, high speed static random access memories.
2. Description of the Prior Art
Numerous processes are now well known for the manufacture of BiCMOS integrated circuits. See, for example, Bastani, et al., "Advanced One Micron BiCMOS Technology for High Speed 256k SRAMs," 1987 VLSI Symposium; Watanabe, et al., "High Speed BiCMOS VLSI Technology with Buried Twin Well Structure," 1985 IEDM. Such processes typically have not been optimized for the manufacture of either the bipolar or the field effect portions of the circuit. For example, in such prior art processes, there is typically a large encroachment by the field oxide used to electrically isolate individual devices from each other. The large field oxide encroachment is undesirable because it decreases device density and degrades performance of the completed circuit. In addition, lower density means that a larger chip size is required for the fabrication of a fixed number of transistors. The larger chip size reduces the yield and therefore increases the cost of the completed product.
Another problem with prior art BiCMOS processes is that the small geometry MOS transistors have been prone to punchthrough, due to the use of relatively thick gate oxides and relatively deep source/drain junctions. In addition, the bipolar devices typically have a high collector-substrate capacitance and a high parasitic capacitance. This undesirably slows circuit operation.
Another disadvantage of prior art BiCMOS processes has been that metal contacts to shallow junctions have been susceptible to leakage. In addition, such prior art BiCMOS processes formed high resistance polysilicon load resistors using techniques which required relatively long resistors, thereby limiting the density of memory cells formed using the BiCMOS process.
Another difficulty with prior art BiCMOS processes was the requirement for tapered sidewalls in contact openings to obtain adequate metal step coverage. The tapered sidewalls undesirably expand the surface area required for a contact, thereby limiting layout density. The reduced layout density carries with it the difficulties mentioned above.
A further disadvantage is the use in prior art BiCMOS processes of relatively long thermal processes. These processes create deep junctions which are incompatible with scaled devices.